CoAsia SEMI and Rebellions Collaborate on AI Chiplet Development

Jul 28, 2025
CoAsia SEMI and Rebellions have announced a partnership to develop next-generation AI chiplets based on the REBEL architecture, with plans for large-scale production by 2026.

CoAsia SEMI and Rebellions have announced a collaboration to develop next-generation AI chiplets based on the REBEL architecture, announced in a press release. The partnership aims to complete development and verification by the end of 2026, with plans for large-scale production to supply both domestic and global AI data centers.

The collaboration involves the integration of CoAsia SEMI's advanced packaging technologies, including 2.5D silicon interposer and manufacturing capabilities, with Rebellions' AI semiconductor expertise. This joint effort is expected to enhance design flexibility, yield, and optimization in power and performance, making it a core technology for AI and HPC servers in data centers.

The agreement also includes participation from global OSAT and IP leaders, aiming to establish a comprehensive ecosystem for the global AI semiconductor market. The companies plan to expand their reach into major markets such as the United States, Europe, and Japan, leveraging a full semiconductor value chain that encompasses fabless design, packaging, OSAT, and IP.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.

Also, consider following us on social media:

AI Chips & Datacenters AI Brief AI Brief (X)
Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

AI Token Webinar

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more

You may also like

Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.