Imec Installs ASML EXE:5200 High-NA EUV System in Leuven Facility
Belgian semiconductor research center imec has received the ASML EXE:5200 High-NA EUV lithography system, announced in a press release. The installation marks the arrival of the world’s most advanced lithography equipment at imec’s 300mm cleanroom in Leuven.
Developed by ASML, the High-NA EUV tool features a numerical aperture of 0.55 and provides unmatched resolution and overlay performance. It is designed to support the development of sub-2nm logic and high-density memory technologies. The system is integrated with imec’s suite of patterning and metrology tools to enable research on next-generation semiconductor manufacturing processes.
Imec stated that the new lithography system will allow its ecosystem partners to accelerate chip scaling and performance improvements in areas such as advanced AI and high-performance computing. The installation follows earlier collaboration between imec and ASML at their joint High-NA EUV Lithography Lab in Veldhoven, the Netherlands.
We hope you enjoyed this article
Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.
Also, consider following us on social media:
More from Data Centers
Oct 16 EverWind Plans 420 Megawatt AI Data Centre in Nova Scotia Oct 16 Gartner Says $3.5 Trillion in AI Infrastructure Spending Faces Impairment Risk by 2030 Oct 16 KBRA Rated Anthropic BB+ Before $35 Billion Chip Financing Oct 16 China Proposes Export Controls for Advanced AI Models and Chips Oct 16 Hitachi Energy and Ansaldo Energia Partner on Data Center Power SystemsSilicon Brief
Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.
Whitepaper
Tensordyne Napier: What If One Rack Could Do the Work of Nine?
Tensordyne
This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.
Read moreYou may also like
E&R Engineering to Show CPO Laser Tools at SEMI West 2026
Cognex Launches In-Sight 1750 Wafer Reader
GS Microelectronics and Teradyne Plan Silicon Valley Chip Test Center
Synopsys and TSMC Expand AI Chip Design Partnership
NovoLINC Launches MaxLINC Thermal Material for AI Chips
Daily AI Brief: the AI news that matters, in your inbox.