Keysight and Intel Foundry Collaborate on EMIB-T Technology for AI and Data Centers
Keysight Technologies and Intel Foundry have announced a collaboration to support Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, aimed at advancing high-performance packaging solutions for AI and data center markets. This collaboration, announced in a press release, focuses on improving communication between chiplets and 3DICs, which is crucial for handling the growing complexity of AI and data center workloads.
The partnership supports the latest interconnect standards, including Universal Chiplet Interconnect Express™ 2.0 and Open Compute Project Bunch of Wires, enhancing design flexibility and reducing development costs. Keysight's Chiplet PHY Designer now offers advanced simulation capabilities for these standards, enabling pre-silicon level validation and streamlining the path to tapeout.
This initiative is part of a broader effort to create a chiplet interoperability ecosystem, which aims to accelerate innovation and ensure reliable high-speed data transfer and efficient power delivery in next-generation semiconductor applications.
We hope you enjoyed this article
Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.
Also, consider following us on social media:
More from Data Centers
Oct 16 Hitachi Energy and Ansaldo Energia Partner on Data Center Power Systems Oct 16 Clivet Unveils Magnetic Bearing Compressor for AI Data Center Cooling Oct 15 Rising rates strain AI data center fundraising Oct 15 Ukrainian Drones Hit Sberbank Data Center Planned for Supercomputer Oct 15 Brightray Signs Letter of Intent for 10 MW Indiana AI Data CenterSilicon Brief
Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.
Whitepaper
Tensordyne Napier: What If One Rack Could Do the Work of Nine?
Tensordyne
This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.
Read moreYou may also like
M31 and Ambiq Develop Low Power Chip IP for TSMC N12e
ITRI Unveils 3.2 Tbps Silicon Photonics Optical Engine
Ricursive Intelligence Details AI System for Chip Design
SEMIFIVE signs $52 million AI accelerator contract
Xsight Labs Introduces 25 Watt E1L DPU for Edge Systems
Daily AI Brief: the AI news that matters, in your inbox.