Mixed-Signal Devices Unveils Advanced Timing Solutions for AI and 5G

Jun 4, 2025
Mixed-Signal Devices has launched a new portfolio of multi-gigahertz timing solutions, offering sub-20 fs jitter and 2 GHz performance, designed for AI, 5G, and aerospace systems.
Mixed-Signal Devices Unveils Advanced Timing Solutions for AI and 5G

Mixed-Signal Devices has launched its latest multi-gigahertz timing and clock portfolio, announced in a press release. This new lineup includes the MS11X0 oscillator and MS15X0 jitter attenuator families, which deliver sub-20 femtosecond jitter and 2 GHz performance. These solutions are designed to meet the demands of AI data centers, 5G base stations, and aerospace systems.

The new timing solutions feature a breakthrough platform built on 28 nm CMOS technology and the company's patented Virtual Crystal™ architecture. This allows for scalable precision, replacing traditional analog limitations with advanced CMOS capabilities. The MS1130 and MS1150 oscillators, along with the MS1500 and MS1510 jitter attenuators, offer ultra-low jitter, robust thermal stability, and programmable configurations, making them ideal for high-speed networking and compute systems.

These devices are engineered to provide reliable performance across harsh environmental conditions, with features such as ±20 ppm thermal stability and compact CMOS packages. The new portfolio is currently available for sampling and will be showcased at the IEEE MTT-S International Microwave Symposium in San Francisco from June 15-20, 2025.

We hope you enjoyed this article

Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.

Also, consider following us on social media:

Free newsletter

Silicon Brief

Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.

Whitepaper

Tensordyne Napier: What If One Rack Could Do the Work of Nine?

Tensordyne

This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.

Read more
Free, six days a week

Daily AI Brief: the AI news that matters, in your inbox.