Synopsys and Broadcom Achieve PCIe 6.x Interoperability
Synopsys has announced a significant milestone in collaboration with Broadcom Inc., achieving interoperability between Synopsys' PCIe 6.x IP solution and Broadcom's PEX90000 series switch. This achievement was demonstrated at PCI-SIG DevCon 2025, showcasing the capability of the PCIe 6.x technologies to operate seamlessly at 64 GT/s, which is crucial for high-performance AI and computing solutions announced in a press release.
The demonstration featured Synopsys' PCIe 6.x IP solution, including PHY and controller, functioning as a root complex and an endpoint with Broadcom's switch. This interoperability is expected to reduce design risks and accelerate the deployment of AI-driven data center systems. The event highlighted Synopsys' commitment to delivering silicon-proven IP solutions that meet the rigorous demands of modern AI workloads.
Broadcom's collaboration with Synopsys marks a significant step forward in the adoption of the PCIe 6.x standard, addressing the growing demands for scalability and performance in AI and high-performance computing environments. This milestone reinforces the readiness of Synopsys' PCIe 6.x IP solution to support next-generation AI infrastructures.
We hope you enjoyed this article
Consider subscribing to one of our newsletters like Silicon Brief or Daily AI Brief.
Also, consider following us on social media:
More from Data Centers
Oct 16 Hitachi Energy and Ansaldo Energia Partner on Data Center Power Systems Oct 16 Clivet Unveils Magnetic Bearing Compressor for AI Data Center Cooling Oct 15 Rising rates strain AI data center fundraising Oct 15 Ukrainian Drones Hit Sberbank Data Center Planned for Supercomputer Oct 15 Brightray Signs Letter of Intent for 10 MW Indiana AI Data CenterSilicon Brief
Weekly coverage of AI hardware developments including chips, GPUs, cloud platforms, and data center technology.
Whitepaper
Tensordyne Napier: What If One Rack Could Do the Work of Nine?
Tensordyne
This Tensordyne whitepaper presents Napier, an inference-focused AI processor and rack-scale system based on the company’s TDN Math logarithmic number system. It examines infrastructure requirements for large mixture-of-experts and agentic models, compares major inference architecture approaches, and details the TDN AIP processor, TDN72 pod, TDN Link fabric, and Napier Ultra configuration. The paper reports simulation-based performance, cost, and accuracy-validation results, including Tensordyne’s projected comparison of one Napier rack with a nine-rack Nvidia Rubin plus Groq deployment; the chip is reported as taped out and in fabrication.
Read moreYou may also like
Cisco and NVIDIA Plan Open 400G Optics Specification
OpenAI and Synopsys Develop GPT-Synopsys for Chip Design
Teledyne LeCroy Releases PCIe 7.0 Protocol Exerciser
Spectrum Adds NVIDIA AI Compute to Its Edge Network
Airoha Details 50G PON AI Gateway Processor
Daily AI Brief: the AI news that matters, in your inbox.