Synopsys Introduces Software-Defined Verification Platforms for AI Chip Design

Synopsys has introduced new software-defined hardware-assisted verification (HAV) platforms and capabilities to accelerate AI silicon development, announced in a press release. The company said the latest updates deliver up to twice the performance and capacity for its ZeBu Server 5 system while adding hardware-assisted test automation features for faster bug detection.

The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms expand emulation and prototyping capacity by two times and include EP‑Ready Hardware for improved performance in mainstream use cases. These enhancements aim to support increasingly complex chip designs across data center and edge applications.

The announcement follows the company's rollout of new software tools to manage AI chip design complexity after its $35 billion acquisition of Ansys, Reuters reported. The integration of these tools allows chip designers to address mechanical and thermal challenges during the design phase, improving efficiency and lowering costs.